The present invention relates generally to analog to digital converters, and more particularly to analog to digital converters comprising a pipelined, delta sigma modulator architecture.
Analog to digital converters (ADCs) provide the link between analog and digital domains. The ADC must be capable of converting analog data to digital data in an accurate manner, appropriate to the bandwidth and resolution requirements of particular application. Digital circuitry has become increasingly prevalent in a wide variety of electronic devices including telecommunications, audio, video, portable/mobile communication transmitters and receivers. Analog components can be eliminated with the corresponding reduction in size, weight, and power consumption by converting from analog to digital signals near the front end of a signal processing train. Converting to digital signals near the front end of the signal processing train usually requires a broad band/high resolution ADC, so there is much demand for ADCs with increased resolution and larger bandwidths.
One type of ADC is called a Nyquist rate converter. The sampling frequency for a Nyquist rate ADC must be at least twice the bandwidth of the input signal, such as for example, a bandwidth of 25 MHz would require at least a 50 MHz sampling frequency. A straightforward implementation of a Nyquist rate ADC is a flash converter where 2n−1 comparators are used to directly measure an analog signal to a resolution of n bits. The flash architecture has the advantage of being very fast, because the conversion occurs in a single ADC cycle. The disadvantage of this approach is that it requires a large number of comparators that are carefully matched and properly biased to ensure that the results are linear. Since the number of comparators needed for an n-bit resolution ADC is equal to 2n−1, limits of physical integration and input loading keep the maximum resolution relatively low. For example, a 4-bit ADC requires 15 comparators, an 8-bit ADC requires 255 comparators, and a 16-bit ADC would require 65,535 comparators.
One technique for alleviating the requirement for the large number of comparators is to use a pipelined ADC. A pipelined ADC divides the conversion task into several consecutive stages (T). For a pipelined ADC, the first stage produces the most significant bits (K-bits) and each successive stage produces the next K-bits, so that T stages would yield T*K-bits of resolution. This process is repeated through as many stages as are necessary to achieve the desired resolution. A typical range for K would be 1–4 bits and in some implementations K may vary between stages.
Each stage requires an analog sample/hold circuit, a K-bit flash converter, a K-bit digital to analog converter, an analog subtract circuit, and an analog multiplier circuit. The digital outputs of each stage must be appropriately delayed and combined to obtain a new digital output word each clock cycle. In practice, each stage of the pipelined ADC must produce at least K+1 bits to obtain K-bits of accuracy. In principle, a pipelined converter with P pipelined stages, each with an M-bit flash converter, can produce a high-speed ADC with a resolution of N=P*M bits using P*(2M−1) comparators. For example, a 2-stage pipelined converter with 8-bit resolution requires 30 comparators, and a 4-stage 16-bit ADC requires only 60 comparators. However, although the Nyquist rate pipelined ADC reduces the number of comparators, some critical analog components are still required, which must be very accurate, such as sample/hold, subtract, and multiplier.
A second type of ADC is an over-sampling converter based on delta sigma modulation. Over-sampling ADCs are used in applications requiring high resolution because the approach permits high resolution without the need for extremely tight tolerances for analog components. The delta sigma modulator ADC combines feedback with an analog integrator to shift the quantization noise to higher frequencies outside the bandwidth of the signal. The digital output is then passed through a low pass filter to remove the quantization noise that has been shifted to higher frequencies. This permits the use of 1 to 4 bit flash ADCs (quantizers) to obtain more bits of resolution after low pass filtering. The increase in the number of bits depends on the over sampling ratio (OSR). The OSR is the ratio of the sampling frequency to twice the bandwidth (Nyquist Frequency) of the input signal. For a conventional first order (one integrator) delta sigma modulator, the signal to noise ratio increases by 9 db (1.5 bits) for each doubling of the OSR. OSRs typically range from 8 to 256, depending on the application.
The pipelined ADC is good for broadband applications, since it needs to sample only at the Nyquist rate, but it is difficult to obtain high resolution because of the component accuracy requirements and the need for many stages. On the other hand, the delta sigma modulator ADC is good for high resolution, but it is difficult to obtain broad bandwidths because of the required OSR.